1. Field of the Invention
The present invention generally relates to voltage controlled oscillators (VCOs), and more particular, to VCOs used as local oscillators on integrated circuit (IC) chips.
2. Background Description
Increasingly, electronic communications, both wired and wireless (e.g., WiFi), are digital. In digital communications a serial data string of ones (“1”s) and zeros (“0”s) modulate a carrier frequency (fc=ωc/2π) that is transmitted unidirectionally or bidirectionally. Bidirectional communications require a transmitter and receiver (transceiver) at each end to transmit/receive the communications signals. A suitable digital communications transceiver also includes a local modulator-demodulator (modem) capability. Modulating and demodulating requires a local radio frequency (RF) source, e.g., a local oscillator (LO), providing a true replica of the carrier frequency.
A tank circuit, a capacitor (C) connected to an inductor (L), oscillates at its resonant or natural frequency (f0, where ω02=1/LC), determined by the tank circuit capacitance and inductance. An ideal tank circuit (just L and C) will oscillate purely sinusoidally at its natural frequency, indefinitely. Since nothing is ideal, all tank circuits include resistance (R). Inductor current lags voltage and capacitor current leads voltage by ninety degrees (90°). Thus, because resistor current is in phase with voltage across the resistor, tank circuit resistance shifts the phase (Δω) in the tank circuit, dampens the tank circuit oscillation, and determines what is known as the tank circuit's Q factor or Q.
Therefore, typical state of the art oscillators require regenerative feedback to maintain oscillation. Phase noise is a measure of signal spread (and Q) and satisfies L(Δω)=4FkTR/VRMS2*(ω0/2QΔω)2, where k is the Boltzman constant, T is the operating or ambient temperature, VRMS is the root mean square of the tank circuit voltage, and F=1+(4γIR/V0π)+8γgmbiasR/9. Also, for communications, phase noise is a critical parameter for measuring data transfer quality and reliability.
Essentially, Q indicates tank circuit efficiency, peak energy stored in the tank circuit (reactance, XL=jω0L and XC=−1/jω0C) with respect to the average energy dissipated (in the tank circuit resistance R) at resonance, i.e., Q=L/RC. Low Q circuits are, therefore, lossy and more heavily damped. Thus, the higher the Q, the closer to ideal the local oscillator tank circuit. All oscillators have some inherent/parasitic resistance, e.g., from wiring, contacts and drivers, that lowers the tank circuit Q. Minimizing this inherent/parasitic tank circuit resistance and parasitic capacitance is a focus of oscillator design, as is otherwise compensating for any residual resistance and parasitic capacitance.
To offset inherent, parasitic resistance, a typical oscillator includes a pair of cross coupled devices (e.g., bipolar transistors, field effect transistors (FETs) or logic gates, such as inverters) connected to an LC tank circuit. The cross coupled devices add negative resistance as the LC oscillates, thereby providing regenerative feedback. However, the cross coupled devices may also add more resistance and/or more capacitance (which shifts the resonant frequency). Further, circuit component age and ambient conditions, e.g., operating voltage and temperature, can alter the characteristics of the oscillator to shift the resonant frequency away from nominal. A typical voltage controlled oscillator (VCO) is a tunable oscillator where a control voltage is adjusted to shift the VCO operating frequency, for example, to re-center the frequency and/or compensate for phase shift. For the state of the art voltage controlled oscillator, either the LC tank still drives output buffers directly or the LC capacitively drives the output buffers through a tapped capacitance network.
FIG. 1A shows a simple example of a typical VCO 50. Each of a pair of identical tank circuits includes inductors 52 and a voltage variable capacitors (varactor) 54. In this example, the inductors 52 are connected to reference or supply voltage (Vdd) at one end and at the other end to varactors 54, which also are connected to, and controlled by, a control voltage (Vcontrol), providing the voltage control. The LC tank circuits 52, 54 are each connected to the drain of one of a pair of cross coupled devices, N-type FETs (NFETs) 56T, 56C and a clock driver or buffer 58. The connection to buffers 58 is directly coupled to the tank LC. Alternately, the devices 56T, 56C may be P-type FETs (PFETs) with appropriate modification, i.e., swapping Vdd and ground.
In VCO 50 the cross coupled devices 56T, 56C, essentially add negative resistance (i.e., device resistance) to the tank circuit. Both the devices in buffers 58 and wiring to the buffers 58, load the tank circuit (i.e., add capacitance and resistance), causing a frequency/phase shift that depends upon Cload. The tank circuit oscillates at a resonant frequency determined by the inductance (L) of the inductors 52 and Cload added to varactor 54 capacitance (C) in response to the control voltage, i.e., Cp1=C+Cload. Bearing in mind that increasing parallel capacitance reduces circuit Q, Qp1<Q0, where Q0 is the VCO Q factor without loading effects. Thus, the load of VCO 50, which is directly connected to the tank circuit, lowers Q to Qp1, and directly affects oscillator frequency and phase noise.
Frequently, a single VCO 50 drives several output loads, which subjects the VCO to frequency drift known as load pushing. So, normally, the LC tank drives output buffers 58. The LC tank also is connected to the cross coupled oscillator devices 56T, 56C. The load on an oscillator may vary significantly from application to application depending on the number and/or size of buffers 58 being driven. For this directly coupled oscillator 50, this variation in tank circuit load can cause significant oscillation frequency variation and add to phase noise.
FIG. 1B shows an example of a tapped capacitance VCO 50′. The tapped capacitance VCO 50′ has reduced load sensitivity because Cload is not directly connected to the tank circuit. Instead, Cload is connected to the tapped capacitance C1, C2, where C1<<C2. In particular, Cload is connected in parallel with capacitor C2 (i.e., additively), and both are connected in series with C1 (inversely additively). The equivalent capacitance CP2 loads the tank circuit according to CP2=C+C1//(Cload+C2). Thus, Cp2<<Cp1 and Q0≈QP2>>QP1.
Getting to this higher QP2, however, required adding the tap capacitors C1 and C2 for each output. Each capacitor C1, C2 requires additional chip area. A typical IC capacitor usually occupies a relatively large part of valuable chip area. This increases chip fabrication costs. Moreover, because wires passing over or adjacent to these capacitors C1, C2, adds parasitics that may introduce cross-talk to couple passing signals into the circuit and that may further change circuit Q in what may be unexpected ways. To avoid these parasitic changes, the area above, below and adjacent to the capacitors may need to be blocked off from wiring, further consuming valuable chip area.
FETs 56T, 56C in the VCOs 50, 50′ of FIGS. 1A-B are state of the art FETs such as the bulk FETs 60 or the silicon on insulator (SOI) FETs 80 shown simple cross-sectional examples of FIGS. 2A-B. A bulk FET 60 is formed in a wafer 62, e.g. a silicon wafer, body doped with a first dopant type, e.g., N-type for NFETs. A well 64 of the opposite dopant type (P-type in this example) is formed in the wafer 62, and although multiple devices may be made in the same well 64, in this example a single device 60 is formed in each well 64. A gate 66 is formed above gate oxide 68 on the wafer 62. Source/drain diffusions (N-type) 70SD are formed adjacent to the gates 66 and a substrate contact 70X is formed to the bulk wafer 62. In a typical CMOS fabrication process, well contact (N-type) 72 is formed when P-type source/drain regions are formed for opposite type devices, i.e., for PFETs. Although not shown here, source/drain extensions typically extend from the source/drain diffusions 70SD to the edge of the gate 66 and a self-aligned silicide (salacide) layer may be formed on the gates 66, diffusions 70SD, well contact 72 and substrate contact 70X to reduce circuit resistance. Wires 74, e.g., metal, vias, etc., are formed selectively on the salacided surface to connect the cross coupled devices together (connecting the gates 66 to diffusions 70) and to provide a bias (i.e., reverse bias) to the well 64 and to the substrate 62. Additional wiring (not shown) is normally formed above the surface in subsequent layers.
Each SOI FET 80 is formed in an island 82 isolated from the wafer 62. The island 82 is body doped substantially identically as well 64 for the bulk FET 60 and may support multiple FETs of the same type. Each island 82 is isolated from the wafer 62 by insulator/dielectric 84, e.g., buried oxide (BOX) and shallow trench isolation (STI). Although shown with a well (body) contact 72, under some circumstances this contact may be omitted, e.g., in the VCO 50 example of FIG. 1. If the body contact 72 is omitted, the device body (i.e., the doped island 82) is allowed to float.
In what is known as a back-gate (body contact) coupled VCO, the tank is capacitively coupled to, and may be cross coupled through, the bodies 72 of the VCO devices 60, 80. An example of a back-gate coupled VCO is provided by Kim et al. “A Very Low-Power Quadrature VCO with Back-Gate Coupling,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 6, JUNE 2004, pp. 952-5.
FIG. 3 shows another example of a back-gate coupled VCO 90, described in more detail by U.S. Pat. No. 7,545,230 to Jong et al. In this example, instead of cross-coupled devices 56T, 56C in FIGS. 1A and 1B, the VCO includes a latch, i.e., a pair of cross-coupled CMOS inverters 92T, 92C. The tank circuit switches the cross-coupled inverters 92T, 92C, which drive the result rail to rail, i.e., between supply (Vdd) and ground, at the resonant frequency. Each inverter 92T, 92C includes a PFET 92P and an NFET 92N. The body contact (70X in FIGS. 2A and 2B) of the PFETs 92P is tied to the supply, i.e., tied body to source. The body of each NFET 92N is DC biased to ground through bias resistors 94. A capacitive network 96, 98 couples the signal from the tank circuit to the body of NFETs 92N.
Since FET turn-on is dependent on threshold voltage (VT), which in part also controls current; and since device VT depends on device source to substrate voltage (VSX); the coupled signal varies each NFETs VT to vary the point at which NFET current flows. Thus, shifting the NFET VT shifts the phase of the tank circuit. The back bias network (resistors 94 and capacitive network 96, 98) is coupled directly to the tank circuit. So, the back bias network itself capacitively and resistively loads the tank circuit, lowering the circuit Q and shifting the resonant frequency.
However, the LC tank still drives the load on these state of the art back-gate coupled VCOs, e.g., 90. Thus, the VCO load, which is primarily capacitive and secondarily resistive and driven by the LC tank, adds capacitance and resistance to the LC. As noted hereinabove, any added capacitance tends to shift the resonant frequency. As also noted, any added resistance lowers the LC tank Q.
Thus, there exists a need for a load insensitive RF oscillator for on-chip use in an IC, e.g., as a local RF source for a wired or wireless (e.g., WiFi) transceiver.